1. Field of the Invention
This invention relates to a semiconductor device of a voltage-driven type that has a low ON-resistance and a rush current protecting function, and is driven at a low voltage.
2. Description of the Related Art
Structures of conventional devices in this field are known as a normally-off type transistor having excellent controllability and low on-resistance at switching time. Such structures are described in, for example, Japanese Laid-Open Patent Publication No. Hei 6-252408.
FIG. 6A is a perspective view showing the structure of such a conventional semiconductor device, and FIG. 6B is its plan view. As shown in FIG. 6A, an Nxe2x88x92-type epitaxial layer 52 is formed on an N+-type semiconductor substrate 51. A plurality of trenches 57 are formed in the epitaxial layer 52 so as to be disposed in parallel to one another at an equal interval from the surface. The substrate 51 is used as a drain pickup region, and the epitaxial layer 52 is mainly used as a drain region 53. The trenches 57 are formed so that the side walls thereof are substantially vertical to the surface of the epitaxial layer 52, and insulating films 56 are formed in the inner walls of the trenches 57. Furthermore, for example, polycrystal silicon (polysilicon) doped with P-type impurities is deposited in the trenches 57. The polysilicon in the trenches 57 is electrically connected to source regions 54, for example, through aluminum (Al) wiring, on the surface of the epitaxial layer 52. Therefore, the P-type polysilicon in the trenches 57 is used as a fixed potential insulated electrodes 55 kept at the same potential as a source electrode S. The epitaxial layer 52 located between the plurality of trenches 57 is used as channel regions 58.
As shown in FIGS. 6A and 6B, a plurality of gate regions 59 are spaced from the source regions 54 and disposed at a fixed interval in the epitaxial layer 52 adjacent to the insulating films 56. As shown in FIG. 6B, each of the fixed potential insulated electrodes 55 has a comb-shape, and the teeth of the comb-shape extend to the right and left sides in the horizontal direction of the drawing with the center portion of the fixed potential insulated electrode 55 aligning in the vertical direction of the drawing (hereinafter referred to as an axial portion). That is, each of the gate regions 59 is formed so as to be overlapped with a part of the end portions of the corresponding comb teeth of the fixed potential insulated electrodes 55 extending from both sides, and in contact with the insulating film 56.
Next, the sectional structure and operation of this conventional semiconductor device will be described with reference to FIGS. 7A and 7B. FIG. 7A is a cross-sectional view taken along line Xxe2x80x94X of FIG. 6B, and FIG. 7B is a cross-sectional view taken along line Yxe2x80x94Y of FIG. 6B.
As shown in FIG. 7A, the regions surrounded by the trenches 57 in the surface region of the epitaxial layer 52 correspond to the channel regions 58, an arrow H represents the thickness of the channels, and an arrow L represents the length of the channels. For example, an Al layer 60 is brought into ohmic contact with the back surface of the N+-type substrate 51 used as the drain pickup region, and a drain electrode D is formed through the Al layer 60. On the other hand, an Al layer 61 is formed on the surface of the epitaxial layer 52 so as to come into ohmic contact with the source regions 54 and the fixed potential insulated electrodes 55, and the potential of the fixed potential insulated electrodes 55 is fixed to the potential of the source electrode S.
As shown in FIG. 7B, a silicon oxide film 62 is deposited on the surface of the epitaxial layer 52 in addition to the surfaces of the gate regions 59. Furthermore, a gate electrode G formed of Al or the like is formed through contact holes provided in the silicon oxide film 62 on the gate regions 59. The broken line in FIG. 7B shows the range of the fixed potential insulated electrodes 55.
Next, the operational principle of the conventional semiconductor device will be described. First, the OFF state of the semiconductor device will be described. As described above, the current path of the semiconductor device includes the N+-type substrate 51 serving as the drain pickup region, the drain region 53 comprising the Nxe2x88x92-type epitaxial layer 52, the Nxe2x88x92-type channel regions 58 located between the trenches 57 in the surface region of the epitaxial layer 52, and the source regions 54 formed on the surfaces of the Nxe2x88x92-type channel regions 58. That is, all the regions are of N-type. This structure may provide a superficial understanding that if a positive voltage is applied to the drain electrode D and the device is operated while the source electrode S is grounded, it is impossible to set the device to an OFF state.
However, as described above, the N-type regions of the source regions 54 and the channel regions 58 and the P-type regions corresponding to the fixed potential insulated electrodes 55 are connected to one another through the Al layer 61 and kept at the same potential. Therefore, in the channel regions 58 around the fixed potential insulated electrodes 55, depletion layers are spread so as to surround the fixed potential insulated electrode 55 due to the difference in work function between P+-type polysilicon and the Nxe2x88x92-type epitaxial layer 52. That is, by adjusting the interval width between the trenches 57 forming the fixed potential insulated electrodes 55, in other words, the channel width H, the channel regions 58 are fully filled with the depletion layers extending from the fixed potential insulated electrodes 55 at both sides. The channel regions 58 fully-filled with the depletion layers become pseudo P-type regions.
With this structure, a PN junction separation structure is formed from the Nxe2x88x92-type drain region 53 and the N+-type source regions 54 by using the channel regions 58 serving as the pseudo P-type regions. That is, since the pseudo P-type regions are formed in the channel regions 58, the semiconductor device is kept at a shutoff state at (OFF state) the initial stage.
Next, the transfer state from OFF to ON in the semiconductor device will be described. First, a positive voltage is applied to the gate electrode G, which is initially at ground voltage. Accordingly, free carriers (holes) are introduced from the gate regions 59. As described above, the free carriers (holes) are-attracted by ionized acceptors and flow into the interface of the insulating films 56. By filling the free carriers (holes) at the interfaces of the insulating films 56 of the channel regions 58, only the ionized acceptors and free carriers (holes) in the P+-type polysilicon regions are paired to form an electric field. Therefore, free carriers (electrons) exist from the farthest region from the insulating film 56 in each channel region 58, in other words, from the center area of the channel region 58, and thus a neutral region appears. As a result, the depletion layers of the channel regions 58 are diminished, the channels are opened from the center regions and the free carriers (electrons) move from the source regions 54 to the drain region 53, so that main current flows.
The free carriers (holes) instantaneously travel along the wall surfaces of the trenches 57 as paths, and the depletion layers spreading from the fixed potential insulated electrodes 55 to the channel regions 58 are diminished. Thus, the channels open. Furthermore, when a voltage of a predetermined value or higher is applied to the gate electrode G, the PN junctions constructed by the gate regions 59, the channel regions 58 and the drain region 53 are forwardly biased. The free carriers (holes) are directly injected into the channel regions 58 and the drain region 53. As a result, a number of free carriers (holes) are distributed in the channel regions 58 and the drain region 53, and conductivity modulation occurs, so that the main current flows with low ON-resistance.
Finally, the transfer state from ON to OFF of the semiconductor device will be described.
In order to turn off the semiconductor device, the potential of the gate electrode G is set to the ground voltage (0V) or negative potential. By the conductivity modulation, a large number of free carriers (holes) existing in the drain region 53 and the channel regions 58 are extinguished, or passed through the gate regions 59 and discharged to the outside of the device. Accordingly, the channel regions are fully filled with the depletion layers again, and become pseudo P-type regions once more, so that the withstanding voltage is maintained and the main current is stopped.
As described above, the conventional semiconductor device is operated by making free carriers (holes) flow into and from the gate regions 59, and thus it is a current-driven type semiconductor device. However, in the case of the current-driven type semiconductor device, it is difficult to drive the semiconductor device because of difficulties such as power loss in a driving circuit or the like.
The invention provides a semiconductor device that includes a semiconductor substrate of a first conduction type and an epitaxial layer of the first conduction type disposed on the semiconductor substrate. At least a part of the epitaxial layer and a part of the semiconductor substrate are configured to function as a drain region. The device also includes a plurality of variable-potential insulated electrodes. Each of the electrodes fills in a corresponding trench formed in the epitaxial layer and includes a semiconductor of a second conduction type. The trenches is substantially parallel to each other, and an insulating film is disposed between each of the electrodes and an inner wall of the corresponding trench. The device also includes a plurality of source regions of the first conduction type formed in the epitaxial layer. At least one of the source regions is disposed between a corresponding couple of the trenches. The device also includes a plurality of gate regions of the second conduction type formed in the epitaxial layer. Each of the gate regions is disposed away from the corresponding source region and adjacent at least a portion of the corresponding insulating film. The gate regions are configured to be at a same potential as the variable-potential insulated electrodes. The device further includes a plurality of channel regions disposed in the epitaxial layer. At least one of the channel regions is disposed between a corresponding couple of the trenches and at least below the corresponding source region.
The invention also provides a semiconductor device that includes a semiconductor substrate having a surface of a first conduction type. A drain region is formed in the surface. The device also includes a plurality of variable-potential insulated electrodes. Each of the electrodes fills in a corresponding trench formed in the surface of the semiconductor substrate and has a semiconductor of a second conduction type. The trenches are substantially parallel to each other, and an insulating film is disposed between each of the electrodes and an inner wall of the corresponding trench. The device further includes a plurality of source regions of the first conduction type formed in the surface of the semiconductor substrate. Each of the source regions is disposed between a corresponding couple of the trenches. The device also includes a plurality of gate regions of the second conduction type formed in the surface of the semiconductor substrate. Each of the gate regions is disposed away from the corresponding source region and adjacent at least a portion of the corresponding insulating film. The gate regions are configured to be at the same potential as the variable-potential insulated electrodes. The device further includes a plurality of channel regions disposed in the surface of the semiconductor substrate. Each of the channel regions is disposed between a corresponding couple of the trenches and at least below the corresponding source region.